This invention relates in general to semiconductor memory devices, and more particularly to semiconductor memory devices including redundant cells for replacing faults within the memory device.
As it is known in the art, during the fabrication of semiconductor memory devices it is possible for a memory device to include defects that will prevent the device from operating properly. These possible defects include short circuits between adjacent columns or rows or open circuits within individual columns or rows of the memory device, as well as non-functional clusters of cells.
These types of defects may be easily identified by a testing procedure after fabrication. A semiconductor memory device with a defect is inoperable, and would have to be discarded. Generally, however, the semiconductor memory devices have been designed to include a redundancy circuit having a number of redundant cells to replace the defective memory cells.
Typically two types of redundancy have been provided. One type is row redundancy. In memory devices which provide row redundancy, the memory device is apportioned into a discrete number of blocks. For each block, an extra set of rows are provided. If, during testing, it is discovered that a row or two adjacent rows or a cluster of cells within the pitch of a pair of rows in a block is defective, the redundant set for the block is substituted for the defective cells. To activate the redundant circuitry, appropriate fuses are included for programming individual decoder circuits to be responsive to the addresses of the defective set of rows.
There are a number of drawbacks associated with providing row redundancy. The first drawback is that it is ineffective against bit-line failures, that is when an entire column of the semiconductor memory device fails. The second drawback is that although at least a pair of rows is often provided as the redundant set for the block, that set may be ineffective to provide sufficient replacement capability for large clustered defects.
A second type of redundancy is to provide redundant columns in the semiconductor memory device. Depending on the width of the memory device, usually at least a pair of redundant columns is allocated to a predetermined number of columns. For example, a memory array having a 64 bit data path may provide a redundant column pair for each byte of information, thereby providing 8 redundant column pairs. Although column redundancy provides a technique for replacing bit-line failures, the available methods of providing column redundancy are complex and therefore do not make optimal use of the available semiconductor area. An additional problem associated with redundant column design is the increased propagation delay through the semi-conductor device caused by the additional redundant logic. Thus, for memory devices in which the redundant column logic is utilized, because the timing of the device is adversely impacted the device may have to be sold at a discount even though it is utilizing more expensive hardware.
It would be desirable to provide a technique for providing redundancy in the semi-conductor device without adversely affecting the propagation delay or area constraints of the semi-conductor device.